1. Field of the Invention
This invention relates to a semiconductor memory device having reprogrammable memory cells, and particularly to an EPROM (Erasable Programmable Read Only Memory) device having a test circuit for testing each of the memory cells.
2. Description of the Prior Art
As shown in FIG. 1, an EPROM memory device includes a plurality of reprogrammable cells 1, i.e., stacked-gate or double gate memory transistors in the illustrated example, arranged in the form of a matrix having rows and columns. As shown, each of the memory transistors is provided at the intersection between the corresponding column and row. Customarily, during the test mode, the memory cells are tested for read and write operations one by one just like during the ordinary use mode. That is, one of word lines 3 is selected by an address signal A.sub.1 -A.sub.n through an X-decoder 2, and at the same time one of bit lines 5 is selected by another address signal B.sub.1 -B.sub.m through a Y-decoder 4, thereby selecting the memory cell 1 located at the intersection of the thus selected word and bit lines for read/write operation.
However, in the case of an EPROM, the programming time required to program a single cell is rather long and in the order of 50 milliseconds. Thus, in accordance with the test scheme in which the write-in and read out operation is to be carried out one cell at a time, an unacceptably long period of time is required. For this reason, although there has been proposed a method for shortening the programming time per cell in the wafer test, the increase in test time for EPROM devices is becoming more and more serious as the memory capacity increases.